is creating complex FPGA projects and miscellaneous electronics/software

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Hello, I'm Kia and I'm an independent programmer working on FPGA-based DSP/RF systems. Currently, I'm focused on a creating an FPGA air interface (PHY/MAC) for GSM -- and I'm making good progress: I just finished making my GMSK modulator fully-synthesizable and I'm getting ready to tackle the receiver and all its challenges; such as multi-symbol detection, carrier/clock synchronisation, and Viterbi convolutional decoding. However, I would like to spend significant time on some side projects as well, in order to gain diverse experience/skills and to build up a substantive portfolio of work. 

With your support, pursuing these goals will be far more viable for me. I currently do not have the disposable income to spend on proper test equipment / tools / supplies; such as a soldering / hot air rework station, a good oscilloscope (this has changed! I have an oscilloscope now! I am so happy and grateful!), and a bench power supply -- but your support will change that. If you have interesting suggestions/ideas about things you want me to work on, please let me know. Likewise, if you would like to make a donation of appropriate test equipment/tools (or funds to buy it), I would be deeply grateful, please get in contact with me if that's the case. I would also be happy to answer and research your specific questions in these (or related) fields as well!

Examples of specific work I want to do:

1) Contribute to Project Trellis to improve the nascent open-source toolchain for Lattice ECP5 FPGAs, with a focus on fully characterising the configuration/bitstream bits for the sysDSP blocks and addressing placement/inference concerns with these DSP blocks (which are very useful for, well, implementing DSP tasks such as filters/correlators/FFTs).

2) Design, implement, and test an FPGA-based 1090ES/ADS-B aircraft transponder. I have already captured 1030MHz Mode-S interrogations (not the replies or ADS-B "extended squitters" on 1090MHz that you might have seen with dump1090) and implemented a rudimentary Costas loop in Python that successfully does carrier-frequency synchronisation on the BPSK-modulated data burst in the Mode-S interrogation:

However, I still would need to implement it in Verilog, alongside enough state machine to:

  • Recognize appropriately-spaced framing P1 and P2 pulses, as well as legacy Mode A/C interrogations
  • Initialise the parameters for the Costas loop at the right time, and
  • Sample bits at the right times
as well as verify checksums on incoming messages, parse Mode-S interrogations, determine if the 24-bit address in the message is ours (or if it's an all-call interrogation), and compose/modulate a reply; along with interfacing with the appropriate sources for position/altitude/heading/ground speed/airspeed information. All of this needs extensive testing, and I probably do want to include an independent monitor CPU to enforce safety-critical invariants such as a duty-cycle limit -- both to avoid damaging the RF power amplifier (not rated for CW) and also to exclude the possibility of a fault in the FPGA or RF chain making the channel non-usable for other users.

3) I think once I've figured out all the moving parts in a GSM PHY and a 1090ES/ADS-B transponder I should have acquired enough DSP/RF experience to make a radar altimeter, which sounds like a fun project.

3) Fault-tolerant three-phase motor controller. The FETs/IGBTs that generate the waveforms fed to three-phase motors can fail and so can the motor windings, but it's possible (I've read papers claiming so, at least) that there's workable methods that can rapidly detect/classify a subset of possible faults and respond accordingly -- if only to avoid catastrophic failure (such as shorting the DC bus voltage) but maybe even driving the motor in a reduced-power mode (maybe using two of three legs of the bridge?).

4) USB-C related projects: such as an USB-C PD sink to retrofit pre-USB-C laptops to enable use with modern USB-C power adapters and batteries. I am thinking of having a bit of logic that can determine which power profile can provide the most power and either negotiate a 9/12/15 volt profile and use a boost converter to generate 20V -- or negotiate 20V if it's available. Similarly, I want to make a USB-C PD data blocker, like the traditional "USB condom" (apparently that's the term for pre-USB-C USB cables that don't have data lines but do have power rails), but that'd preserve power negotiation without allowing for any kind of data exchange.

5) Implement a modern header compression scheme (like RoHC, which is used in LTE's PDCP layer, but which hasn't seen much use in open-source systems) to provide better bandwidth/latency with lower overhead in Wireguard, as well as implement obfuscation (think Tor pluggable transports) schemes to better evade DPI systems. I plan to do so without introducing significant changes to the Wireguard core codebase and without introducing hazards such as compression oracles.

6) Make versions of network-facing utilities in memory-safe languages, such as procmail, fetchmail, and dhcpcd. Modern email handling/filter tools in Haskell would be nice -- such as an interpreter for the Sieve DSL to replace procmail -- which would obviate any kind of Shellshock-style vulnerabilities. Similarly, I would like to implement a fast dhcp client in a memory-safe language that uses techniques such as those in RFC 4436 and per-SSID/gateway-MAC caching to rapidly get an address.
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